Special call for Short Term Collaboration Grants

Closed

Start: Sept. 6, 2019
Deadline: Nov. 8, 2019
Budget: EUR 40 000

Funding for Short Term Collaboration Exchanges in HPC

Eurolab4HPC is a Coordination Action funded by the European Commission under H2020 with the bold commitment to build the foundation for a European Research Center of Excellence in High-Performance Computing (HPC) Systems.

A funded Short Term Collaboration typically lasts 3 months and needs to end by 20 April 2020. The objective of the instrument is to foster tight integration among research teams from multiple communities working across all levels: hardware, architectures, programming and applications, in alignment with the goals of the Eurolab4HPC Vision. Each proposal should contain representatives from multiple research communities across the whole system stack, including strong commitment from the user communities. The grants will provide funding for short cross-discipline visits, targeted at PhD students, post-doctoral researchers and academics to work on a common project in different layers of the compute stack. Funding is available for independent small studies and benchmarking activities to capture requirements, metrics and opportunities to improve the platforms and technologies. A short term collaboration grant has a maximum budget of 5 000 EUR and will be paid as a daily allowance of 55 EUR for max. 91 days. Half of the Eurolab4HPC grant will be paid upon receival of a grant agreement signed by the grantee, the host and home institution. The second half of the grant will be paid upon submission of a public summary of the activity that will be published on the Eurolab4HPC website. Final documents need to be submitted by 21 April 2020.

Only proposals where either the home or host institution of the applicant is a Eurolab4HPC member, are eligible for the grants. A list of Eurolab4HPC members can be found on eurolab4hpc.eu/community.

The evaluation be done by at least two external independent experts selected by the steering committee under a Non-Disclosure Agreement (NDA), and without conflict of interest with the proposers. The evaluation process will be composed of five steps: (i) eligibility check, (ii) review by external experts, (iii) consensus meeting chaired by the partner in charge of the call, (iv) decision to grant the best proposals by the steering committee, (v) feedback about the outcome of the evaluation process to all the proposers. All applicants will receive information about the outcome of their application by 30 November 2019.

See the attached instructions and proposal template for more details. The proposals have to be submitted via the Eurolab4HPC website no later than on 8 November 2019. The funding period after proposal acceptance is expected to start at the earliest on 1 December 2019.

Funded projects

Title	Team
Toward a New Generation of Sparse Solvers	From University of Illinois at Urbana-Champaign; to Imperial College	Luke Olson
Searching for the optimisation strategies of HPC software	From University of Münster; to University of Edinburgh	Johannes Lenfers	Searching for the optimisation strategies of HPC software Johannes Lenfers From University of Münster; to University of Edinburgh We provide a generic exploration framework applying heuristic search algorithms to search for optimisation strategies f HPC software. Therefore, we use the ELEVATE language to describe optimisation stratefies defining a search space while expressing the computation as RISE program. However, the evaluation process was not finished. A publication about this work was planned. The visit was cut short due to the COVID-19 pandemic.
Evaluation of StarPU task-based programming model in an application targeting exascale computing systems	From NTUA; to Inria	Georgios Tzanos	Evaluation of StarPU task-based programming model in an application targeting exascale computing systems Georgios Tzanos From NTUA; to Inria The result of the work done during this mobility shows that the performance in the application with StarPU is almost the same with native application despite the overhead of the StarPU, while in the same time we gain a lot in matter of maintainability of the code. We accomplished the integration of StarPU having a better scheduling for the tasks trying to achieve pipelining parallelization.
Innovative HPC cooling	From Politecnico di Milano; to EPFL	Federico Terraneo
Evaluation of genome sequencing workloads using SVE	From BSC; to ARM	Rubén Langarita	Evaluation of genome sequencing workloads using SVE Rubén Langarita From BSC; to ARM During my stay at Arm, I have ported the application BWA-MEM2 to SVE, the new vector extension of Arm. Initially, BWA-MEM2 was written using SSE intrinsics, a vector extension of Intel. Some intrinsics could be replaced straight forward, such as the add instructions, that has a direct replacement in the SVE ISA, while other replacements were harder. In order to replace intrinsics that have a direct translation, I used an auxiliary file “sse2sve.h”, where inline functions that replace SSE intrinsics by SVE intrinsics are declared. More complex replacements I executed directly in the code. The second objective was to set up the infrastructure to use Gem5 on a server executing BWA-MEM2. In order to do it, we need the following: - A disk image with the binary and the inputs inside. - Some scripts to execute on a server all the experiments. The scripts allow to execute the application with different vector lengths, memory bandwidth, vector units… - Code inside the application to take checkpoints in order to obtain statistics of the different parts of the application. I have managed to set up this infrastructure. However, I am having some problems after restoring checkpoints while the application is running. I hope to solve this problem soon and start running simulations.
A Fast and Composable Simulation Infrastructure	From NTNU; to EPFL	Truls Asheim	A Fast and Composable Simulation Infrastructure Truls Asheim From NTNU; to EPFL I made contributions to the development of QFlex ranging from bug fixes to feature proposals and infrastructure improvements which makes it easier to run and manage simulations. Additionally, I helped with testing the new release of QFlex to ensure that it was functional. The outcome of this work helped improve the quality of QFlex and ensured that it remains a widely applicable tool for usage scenarios not covered by the group where the primary development is happening.
On Resilience of Stochastic Computing under Aggressive Undervolting	From University of Teheran to BSC	Kamyar Gaviki	On Resilience of Stochastic Computing under Aggressive Undervolting Kamyar Gaviki From University of Teheran to BSC The work done focused on three aspects: (1) We stimulated the training process of XNORnet by considering the use of RAMs with voltage underscaling-related faults. The aim of this work was to understand the behavior of the network in the presence of faults. (2) Modeling of the fault pattern of undervolted RAMs using Generative Adversarial Networks (GANs). (3) Investigating the effect of the aggressive voltage underscaling of FPGA LUTs in the computational accuracy of stochastic computing applications.